In integrated circuit (IC) design, preforming an accurate statistical analysis of rare circuit failure events typically involves lengthy calculations performed over large samples of a multiple dimensional parameter space. The statistical analysis typically involves MC simulations of the IC design using normalized distributions for each of a plurality of random variables involved in IC fabrication according to a foundry where the IC is fabricated. The problem of obtaining accurate statistical samples becomes more acute for high yield estimation of IC designs. To increase the accuracy of a statistical model, current solutions commonly increase the size of the sample set for MC simulations, thereby creating a bottleneck for turnaround time in the design process.
It is desirable to develop a method and a strategy to reduce the size of the sample set for MC simulations, while at the same time obtaining equal or better accuracy for the performance of an IC design.
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